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A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

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4 Author(s)
Jie Wu ; Dept. of Modern Phys., Univ. of Sci. & Technol. of China, Hefei, China ; Yichao Ma ; Jie Zhang ; Mingpu Xie

A low-jitter clock is essential to achieve high performance in a large scale system of distributed sensors. We propose to use a low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks. The new system called digital distributed synchronous clock (DDSC) can reduce the jitter to 14.6 ps, a 60% reduction from 36.5 ps in a traditional PLL. When these two clocks are used as the source for a 24-bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) decrease dramatically from -106 dB with PLL to -117 dB.

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Nuclear Science, IEEE Transactions on  (Volume:57 ,  Issue: 2 )