Referenced Items are not available for this document.
A low-jitter clock is essential to achieve high performance in a large scale system of distributed sensors. We propose to use a low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks. The new system called digital distributed synchronous clock (DDSC) can reduce the jitter to 14.6 ps, a 60% reduction from 36.5 ps in a traditional PLL. When these two clocks are used as the source for a 24-bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) decrease dramatically from -106 dB with PLL to -117 dB.
Published in:
Nuclear Science, IEEE Transactions on
(Volume:57
,
Issue:
2
)
Date of Publication: April 2010
- Page(s):
- 589 - 594
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 11228912
- Digital Object Identifier :
- 10.1109/TNS.2009.2037321
- Date of Current Version :
- 12 April 2010
- Issue Date :
- April 2010
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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