By Topic

A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jie Wu ; Department of Modern Physics, University of Science and Technology of China, Hefei, Anhui, China ; Yichao Ma ; Jie Zhang ; Mingpu Xie

A low-jitter clock is essential to achieve high performance in a large scale system of distributed sensors. We propose to use a low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks. The new system called digital distributed synchronous clock (DDSC) can reduce the jitter to 14.6 ps, a 60% reduction from 36.5 ps in a traditional PLL. When these two clocks are used as the source for a 24-bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) decrease dramatically from -106 dB with PLL to -117 dB.

Published in:

IEEE Transactions on Nuclear Science  (Volume:57 ,  Issue: 2 )