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A Fully Fledged TDC Implemented in Field-Programmable Gate Arrays

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5 Author(s)
Jinhong Wang ; Dept. of Modern Phys., Univ. of Sci. & Technol. of China, Hefei, China ; Shubin Liu ; Qi Shen ; Hao Li
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The motivation of this paper is to implement a fully fledged time-to-digital converter (TDC) in a field-programmable gate array from Xilinx Virtex 4 family with self-test and temperature variation compensation features. The TDC resolution is temperature and supply voltage dependent which, to a large part, is compensated. A self-test procedure, which covers a temperature range of 30 °C to 60 °C is used to determine the compensation constants. After compensation and integral nonlinearity (INL) calibration, the TDC presents a timing resolution of 25 ps RMS or 50 ps per LSB. A total of 9 channels TDCs are implemented in a single FPGA.

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Nuclear Science, IEEE Transactions on  (Volume:57 ,  Issue: 2 )