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Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

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5 Author(s)
Conway, P. ; Adv. Micro Devices, Sunnyvale, CA, USA ; Kalyanasundharam, N. ; Donley, G. ; Lepak, K.
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The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.

Published in:

Micro, IEEE  (Volume:30 ,  Issue: 2 )

Date of Publication:

March-April 2010

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