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With the advancement in communication industries going at a rapid pace, the crucial role of EDA (electronic design automation) tools in virtually every aspect of communication circuit design, fabrication and testing is inevitable. Semiconductor scaling limits for communication devices are forcing designers to look in to novel circuit and design techniques which necessitates for greater modeling complexity and accuracy in EDA tools. In this paper we have proposed two algorithms for performance evaluation of transmission lines which to the best of our knowledge is not proposed elsewhere as per our literature survey conducted. The first is called Sequential Search based test sequence generation algorithm used for generating optimum test sequence for the circuit under test (CUT). The second is called hybrid fault based testing algorithm used for detecting both parametric and catastrophic faults which uses optimized sequence generated by the first algorithm as the input. The Figure of Merit (FOM) for the first algorithm gives the measure of all the faults for a particular test and FOM for the second algorithm gives the measure of all the tests for a particular circuit. The performance analysis of the newly proposed algorithms were done using a unit communication transmission line used as the CUT. A comparison of the proposed algorithms were done with the previous researches in the same field. The paper also gives a comparison of performance evaluation of the unit communication transmission line done using multiple EDA tools like VHDL-AMS, PSPICE & SystemC.