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Minimizing FPGA interconnect delays

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3 Author(s)
Brown, S. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Khellah, M. ; Vranesic, Z.

Optimizing FPGA routing architectures for speed performance also involves improving the CAD tools for mapping circuits. We provide a detailed example of how to design FPGA architectures by examining several important issues associated with interconnect resources for FPGAs that use SRAM programming technology. Our experiments examine two important metrics: the speed performance of implemented circuits and the effective use of available interconnect resources. The goal is to improve upon FPGA speed performance by decreasing delays associated with the interconnect. Our results are most directly applicable to FPGA architectures similar in style to the Xilinx XC4000 series. However, some significant results are of a more general nature and perhaps applicable to other styles of FPGAs as well. In addition to routing architectures, we address the CAD tools that allocate these routing resources to implement circuits

Published in:

Design & Test of Computers, IEEE  (Volume:13 ,  Issue: 4 )

Date of Publication:

Winter 1996

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