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A simulator for at-speed robust testing of path delay faults in combinational circuits

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2 Author(s)
Yuan-Chieh Hsu ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; S. K. Gupta

Conditions are derived for robust testing of a path delay fault via a sequence of vectors applied at-speed. A simulator has been developed that uses the above conditions, along with the knowledge of paths that are robustly tested by the previous vectors, to determine the fault coverage obtained by such testing. The results demonstrate that the existing fault simulators can overestimate robust path delay fault coverage by 5-15%

Published in:

IEEE Transactions on Computers  (Volume:45 ,  Issue: 11 )