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A Physical Model for Fringe Capacitance in Double-Gate MOSFETs With Non-Abrupt Source/Drain Junctions and Gate Underlap

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2 Author(s)
Agrawal, S. ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA ; Fossum, J.G.

For the first time, the inner and outer components of the parasitic gate-source/drain (G-S/D) fringe capacitance in nanoscale double-gate (DG) metal-oxide-semiconductor field-effect transistors, with nonabrupt S/D-body junctions that define effective G-S/D underlap, are physically modeled in terms of the device structure. The model relates the fringe capacitance to the device short-channel effects as governed by the underlap and, hence, gives insights on the effective channel length. The model is verified by numerical simulations of DG devices with varying device parameters, including the dielectric constant of the G-S/D spacer.

Published in:

Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 5 )