Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system

In order to investigate the performance potential of three-dimensional integrated circuits (3-D IC's) for high performance computer systems a comparative study of the interconnect structure of a RISC processor/cache system is presented. The wiring structure, wiring dimensions and line drivers are optimized for 3-D system alternatives. The realizations are compared to a conventional printed circuit board (PCB) and a typical multichip module (MCM) implementation of the system with respect to cache access time and power dissipation. The impact of electrical parameters of interconnection lines as well as associated package parasitics on second level cache read access is investigated. Case studies show reductions of effective switching capacitances of more than an order of magnitude and reductions of second level cache access time of over 30% for optimized 3-D systems compared to conventional PCB realizations.