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Fully-gated ground 10T-SRAM bitcell in 45 nm SOI technology

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4 Author(s)
T. Song ; Georgia Electronic Design Center (GEDC), School of Electrical and Computer Engineering, Georgia Institute of Technology, 85 5th Street NW, Atlanta, GA ; S. Kim ; K. Lim ; J. Laskar

A novel 10T-SRAM employing a fully-gated grounding scheme (10T-RGND) to limit a memory bitcell (MC) subthreshold leakage current (IOFF) in a 45 nm SOI technology is presented. The source voltage of the read-port of 10T-RGND is selectively grounded by a row decoder only when it is accessed, while those of inactive MCs are forced to a supply voltage (VDD). The number of stackable MCs per bitline (BL) of 10-RGND is increased by 10??, 40%, and 3.5?? compared to the conventional 6T, the leakage current-compensating 8T (8T-LC), and the conventional 10T, respectively, at 1.0 V, 125??C, and fast corner process. The total leakage current of 10T-RGND is 6% less than 8T-LC, 17% less than 10T, but 22% larger than 6T in simulation.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 7 )