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Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/Sec pipeline ADC

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3 Author(s)
Santosh, M. ; IC Design Group, Central Electron. Eng. Res. Inst., Pilani, India ; Behera, K.C. ; Bose, S.C.

This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 ??m Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1 mV, SNR of 60 dB. The layout of the sample hold circuit occupies an area of 0.007 mm2 and consumes 1.7 mW of power.

Published in:

Emerging Trends in Electronic and Photonic Devices & Systems, 2009. ELECTRO '09. International Conference on

Date of Conference:

22-24 Dec. 2009

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