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Static Test Data Volume Reduction Using Complementation or Modulo- M Addition

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2 Author(s)
Irith Pomeranz ; School of Electrical and Computer Engineering, Purdue University, W. Lafayette ; Sudhakar M. Reddy

Both test compaction and test data compression methods provide an opportunity for a tester to apply modified versions of each test, in addition to the original test. We take advantage of this opportunity to achieve additional test data volume reductions. One way to modify a test is to complement some or all of its bits. We represent the way in which modified tests will be obtained by a complementation vector. Experimental results demonstrate that, even when a test set has minimum or close-to-minimum size, the use of a complementation vector allows us to reduce the size of the stored test set further, and almost always below the known lower bound on the size of a test set. The use of a complementation vector is equivalent to a modulo-2 addition operation. We generalize it to modulo- M addition, for a constant M ≥ 2. With modulo-M addition, each stored test yields up to M tests. It is thus possible to reduce the size of the stored test set even further.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 6 )