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Miniaturization of hybrid integrated buck converters is impeded by the difference in growth laws in current rating for silicon and for inductors as current rating increases. In the 20 A range, this leads to the attractive feasibility of planarizing the output inductor as the largest component by utilizing low-temperature cofired ceramic technology in the form of the (magnetic) substrate to carry the rest of the converter circuit. The presence of a magnetic substrate below the circuitry creates additional parasitic inductances, which results in low-frequency oscillations. From simulation, the presence of a conductive shield reduces trace inductances and improves circuit performance. There is a minimum shield thickness required to minimize losses associated with ringing. High-shield conductivity is necessary to lower the trace inductance and minimize power loss. Traces should be placed close to the shield to minimize inductance. Experimental results on converters with ceramic-based shield layers and organics-based shield layers bear out the theoretical expectations and establish the practical viability of the proposed hybrid integration technology.