By Topic

Enhancement of CMOSFETs Performance by Utilizing SACVD-Based Shallow Trench Isolation for the 40-nm Node and Beyond

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Yao-Tsung Huang ; Institute of Microelectronics, Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan, Taiwan ; San-Lein Wu ; Shoou-Jinn Chang ; Chin-Kai Hung
more authors

This paper reports an improved densification anneal process for sub-atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance CMOSFETs performance for 40-nm node and beyond. The improved STI densification process is demonstrated to generate a lower compressive stress in the active area as compared to the Standard STI process used in 40 nm technology. For nMOS devices with the improved densification process, the reduction of STI compressive stress is beneficial to the electron mobility and leads to an enhancement of on-current (ION ). In addition, the ION enhancements would significantly increase with shrinking the device dimensions (gate width and source/drain length). On the other hand, the improved densification process would not degrade the pMOSFET's performance resulting from the very small piezoresistance coefficients for 〈1 0 0〉 channel direction. The superior junction leakage characteristics for the junction diodes with the improved anneal process can further verify the lower STI-induced compressive stress due to the less energy bandgap narrowing. Hence, the improved STI process can be adopted in 40-nm CMOS technology and beyond, where device structures have very small active areas.

Published in:

IEEE Transactions on Nanotechnology  (Volume:10 ,  Issue: 3 )