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The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12% improvement in transconductance and 9% enhancement in on-state current for nMOSFETs with a source/drain length (LS/D) of 1.76 ??m and W = 0.5 ??m. The characteristics of the SMT device become more sensitive to the layout geometry as LS/D and W are down to 0.5 and 0.25 ??m, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1/f noise in the SMT device can be properly interpreted by the unified model.