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This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) circuits, which can operate in a single-phase power clock. All the circuits except for the storage cells use improved CAL circuits. The storage cell is based on the conventional memory one. For a comparison, a conventional register file is also realized. Full-custom layouts are drawn, which is realized using TSMC 0.18 Â¿m process, and the net-lists are extracted from their layouts. The post-layout simulations have been performed. The results show that the single-phase adiabatic register file can work very well, illustrating an overall power reduction of about 63% compared with the conventional one at 100 MHz.