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Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs

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3 Author(s)
Chih-Sheng Hou ; Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan ; Jin-Fu Li ; Che-Wei Chou

Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC'02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm.

Published in:

Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on

Date of Conference:

13-15 Jan. 2010