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Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC

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4 Author(s)
Diem Tran ; Fac. of Electron. & Telecommun., Univ. of Sci., Ho Chi Minh City, Vietnam ; Thi To ; Thuan Huynh ; Phuong Nguyen

A flexible hardware accelerator for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real- time image compression and recognition applications. In the system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. The architecture allows using look up tables (LUTs), single-instruction multiple data (SIMD) and two-stage pipeline architecture. This leads to high speed operation suitable for real-time applications. On the other hand, over the last ten years or so, face recognition has become a popular area of research in computer vision and one of the most successful applications of image analysis and understanding. A number of statistical analysis methods have showed their efficiencies in recognition applications. Thus, in this research, an improved method for face recognition using principal component analysis (PCA) and vector quantization (VQ) have been developed as a component of SoPC using a DSP FPGA Development Kit, Stratix II Edition from Altera.

Published in:

Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on

Date of Conference:

13-15 Jan. 2010