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Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

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7 Author(s)

A multi-phase 1 GHz charge pump in 32 nm logic process demonstrates a compact area (159 × 42 ¿m2) for boosting supply voltage from twice the threshold voltage (2 Vth) to 3-4 Vth. Self contained clocking with metal-finger flying capacitors enable embedding voltage boost functionality in close proximity to digital logic for supplying low current Vmin requirement of state elements in logic blocks. Multi-phase operation with phase separation of the order of buffer delays avoids the need for a large storage reservoir capacitor. Special configuration of the pump stages to work in parallel enables a fast (5 ns) output transition from disable to enable state. The multi-phase pump operated as a 1 V to 2 V doubler with >5 mA output capability addresses the need for a gated power delivery solution for logic blocks having state-preservation Vmin requirements.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 4 )

Date of Publication:

April 2010

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