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A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS

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5 Author(s)
Kangmin Hu ; School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA ; Tao Jiang ; Jingguang Wang ; Frank O'Mahony
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This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2 Gb/s data rate with BER < 10-12 across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V, 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6 GHz. The total area of each receiver is 0.0174 mm2, resulting in a measured power efficiency of 0.6 mW/Gb/s.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:45 ,  Issue: 4 )