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Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology

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3 Author(s)
Tobias Erlbacher ; Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Erlangen, Germany ; Anton J. Bauer ; Lothar Frey

In this letter, we report on the reduction of device resistance by up to 36% in lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on a state-of-the-art LDMOS field-effect transistor with a reduced-surface-field extension (buried p-well) for high-voltage applications used for standard IC and ASIC manufacturing processes. Because the well implants can remain unchanged, only a few additional process steps are required for manufacturing such a device. By a straightforward combination of trench- with planar-gate topology, the device resistance can be reduced from 145 to 94 m????mm2 for the underlying 50-V LDMOS device while fully maintaining its specified blocking properties. The depth of the trench gates just slightly influences the electrical device properties, demonstrating the robustness of trench-gate integration into an existing planar-gate technology.

Published in:

IEEE Electron Device Letters  (Volume:31 ,  Issue: 5 )