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Energy-Aware Interconnect Resource Reduction Through Buffer Access Manipulation for Data-Centric Applications

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3 Author(s)
Woohyung Chun ; Dept. of Electr. & Comput. Eng., SUNY - Stony Brook Univ., Stony Brook, NY, USA ; Sungroh Yoon ; Sangjin Hong

This paper presents a methodology for reducing interconnect resources in reconfigurable platforms such as field-programmable gate arrays (FPGAs). This methodology utilizes the techniques developed for the buffer-based dataflow, a new design representation suitable for implementing data-centric applications in a reconfigurable platform. In a buffer-based dataflow, nodes correspond to processing blocks and buffer controllers represent the interconnects between the processing blocks. Since we can isolate the functional execution and data transfer of each node by using buffer controllers, a buffer-based dataflow is helpful for reducing overall design time and for increasing reconfigurability. In this paper, we propose a sharing methodology that can reduce the buffer memory and the number of buses used in the realization of a buffer-based dataflow. By reducing the resources allocated to buffer controllers, we can achieve interconnect resource reduction. The proposed sharing methodology can increase the dynamic energy consumption due to the increased port-loading capacitance. By using the energy consumption model determined by the costs of buffers and buses, we investigate whether the sharing case with the minimum resources corresponds to the sharing case consuming the minimum energy or not. We evaluate the proposed sharing methodology with the dataflow graphs representing data-centric applications such as SIRF, IPv4, MC-CDMA transmitter and receiver.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 5 )

Date of Publication:

May 2011

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