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Use of lead-free solders such as Sn/Ag/Cu results in exposure of printed circuit boards to higher temperatures during assembly compared with eutectic tin-lead solder. If the thermo-mechanical and electrical properties of the laminate materials get affected by exposure to this higher temperature, that may impact the performance and reliability of the circuit board. Variations, if any, in laminate material properties before and after board assembly should be considered in the selection of appropriate laminates. The board and system designers need to be cognizant of such variations and account for them during laminate selection for an application. This paper presents guidelines for laminate selection along with the process used to derive the guidelines. The process includes measurement of key material properties (glass transition temperature, coefficient of thermal expansion, decomposition temperature, time-to-delamination, water absorption, flammability, dielectric constant, and dissipation factor), and their responses to lead-free soldering assembly conditions. A range of commercially available FR-4 printed circuit board laminate materials, classified on the basis of glass transition temperature (high, medium, and low), curing agents (dicyandiamide and phenolic), flame retardants (halogenated and halogen-free), and the presence of fillers, are included in the measurements. The measurements are conducted in accordance with IPC-TM-650 test methods before and after exposure to multiple lead-free soldering profiles. The extent of variations in the properties due to lead-free soldering exposures are reported and analyzed as a function of classification parameters. The causes behind the variations in material properties are investigated by Fourier transform infrared spectroscopy analysis and a conjunctional property analysis. This study also suggests that the preconditioning steps specified in the IPC test methods should address the initial moisture content of the laminate- - test samples in material property measurement tests, otherwise significant errors can be introduced.
Electronics Packaging Manufacturing, IEEE Transactions on (Volume:33 , Issue: 2 )
Date of Publication: April 2010