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To reduce manufacturing cost, lead time, and process complexity, an embedded-active approach that targets rapid prototyping and low-volume production in micro-system packaging is being developed. The approach involves a rapid prototyping of micro-system packaging by a data-driven chip-first packaging process using direct printing of nano-particle metals. In the chip-first process, bare dice are first embedded into a copper or stainless steel carrier substrate, fixed by filling the gap between the chips and the substrate with thermoplastic adhesives, and planarized to a common planar surface. On the coplanar substrate, polyimide film is laminated to form a dielectric layer. Through the dielectric layer to the chip metal pads, micro vias are drilled by laser ablation. The vias are filled with nano-particle silver (NPS). The NPS is deposited by screen printing or aerosol-jet printing and an electrical circuit is formed. This packaging approach is a dry process and it does not require any photo masks for circuit patterning, resulting in reducing packaging turn-around time from months to days. It is also less limited by substrate composition and morphology, eliminates the need for special chip processing such as flip chip solder bumps, and permits using any chip technology and any chip supplier allowing mixed devices. The embedded-active process with NPS avoids the extreme processing conditions required for standard IC fabrication such as wet chemistry processing and vacuum sputtering. The NPS can be sintered at plastic-compatible temperatures as low as 230?C to form material nearly indistinguishable from the bulk metal. The embedded-active packaging shows good reliability performance in terms of thermal shock, which is performed in the range of -40?C and 125?C. These results represent an important step to a system packaging characterized by high-density, low-cost, and data-driven fabrication for rapid package prototyping. This paper presents details of the rapid prototy- - ping process sequence, an initial reliability characterization of the package architecture, and a failure mode analysis of the packages.