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Simulation and generation of IDDQ tests for bridging faults in combinational circuits

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2 Author(s)
S. Chakravarty ; Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA ; P. J. Thadikaran

In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating IDDQ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that the problem of computing IDDQ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable, and, even under some pessimistic assumptions, a complete IDDQ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults

Published in:

IEEE Transactions on Computers  (Volume:45 ,  Issue: 10 )