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A comparison is made of the performance of silicon bipolar and AlGaAs/GaAs heterojunction bipolar technologies for high-speed ECL circuits. Gate delays are calculated for state of the art technologies using a quasi-analytical equation which expresses the gate delay in terms of all the time constants in the circuit. Transistor parameters are used as input to the gate delay expression and these are calculated using either device simulation programs or approximate analytical expressions. A one to one comparison is made possible by the use of an idealised but realistic, transistor layout compatible with both technologies. For an emitter width of 1Â¿m, a collector current of 2 Ã 104A/cm2, and a unity fan-out, gate delays of 26.9 and 12.3ps are predicted for silicon and AlGaAs/GaAs technologies respectively. On scaling to 0.4Â¿m geometries, these delays decrease to 17.2 and 11.4ps. The gate delay expression is used to identify the dominant time constants of the circuit, and hence the most promising options for process and circuit optimisation.
Date of Conference: 13-16 Sept. 1988