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Poly-Buffered LOCOS (PBL) has been widely used as advanced isolation processfor active devices in submicron integrated circuits, since a reduced lateral encroachment compared to the standard LOCOS can be achieved [1, 2]. As the device scaling down is pushing furthermore this isolation technology towards much tighter geometries, a formation of pits in the active area after nitride and polysilicon removal has been observed and recently reported . The pits in the active areas are formed during the polysilicon etch back, and they are due to the voids in the polysilicon layer itself, that are generated during field oxidation . Aim of this work therefore, is the characterisation of the voids formation as a function of different process parameters. A model is proposed which explains by a stress induced silicon diffusion mechanism the voids formation in the poly buffer layer. Finally, process conditions are proposed to guarantee a ``voids-free'' PBL isolation, allowing to realise a PBL isolation scheme that could fulfil the ULSI CMOS future generation technology requirements.