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Technology and Device Design Constraints for Low Voltage-Low Power Sub-0.1 μm CMOS Devices

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1 Author(s)
Koyanagi, M. ; Res. Center for Integrated Syst., Hiroshima Univ., Higashi-Hiroshima, Japan

The device structure and the device design methodology to achieve the low voltage-low power sub-0.1 μm MOS devices are discussed. It is shown in the simulation that it is difficult to simultaneously satisfy two requirements to suppress the short channel effect and to improve the device performance in the sub-0.1 μm devices. It is experimentally demonstrated that the short channel effect can be sufficiently suppressed by employing the double punchthrough stopper structure even in the sub-0.1 μm devices with the gate length of 0.07 μm if the reduced improvement of the device performance is allowed.

Published in:

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Date of Conference:

13-16 Sept. 1993