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Design and Characterisation of the Well module for a 6 transistor CHOS SRAM cell in a 0.5 μ=m lithography CMOS technology

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3 Author(s)
Le Mouellic, C. ; MATRA MHS, Nantes, France ; Le Neel, O. ; Rodde, K.

The design of a 6 transistor SRAM cell with 0.5 μm layout rules requires an N+ to P+ spacing across the well edge in the order of 2 μm. Punchthrough and latchup sensitivity are the major factors which limit the reduction of this spacing. The process reported in this paper solves the problem of the p-type implant with its lateral diffusion at the same time the number of masking steps of the generation of the wells is reduced. Using I-line lithography with 0.5 μm resolution, SRAM cells with a spacing of 2.1 μm have been characterized and shows good isolation behaviour with low subthreshold currents.

Published in:

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Date of Conference:

13-16 Sept. 1993