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CMOS latch-up parameters are experimentally studied in the context of deep submicron technology optimization. Holding voltage and triggering current values are measured for both various design rules (N+/P+ distance, structure width) and various process conditions (epitaxial thickness, substrate resistivity, well dose). It is demonstrated that with diffused well, latch-up free behavior can be obtained down to 2 μm N+/P+ distance. This immunity to latch-up is ensured either by a holding voltage greater than power supply voltage or by triggering currents high enough.