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Process and Design Considerations for Latch-Up Optimization on Deep Sub-Micron CMOS Technology

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3 Author(s)
Leroux, C. ; DMEL-CENG, LETI (CEA - Technol. Av.), Grenoble, France ; Guegan, G. ; Lerme, M.

CMOS latch-up parameters are experimentally studied in the context of deep submicron technology optimization. Holding voltage and triggering current values are measured for both various design rules (N+/P+ distance, structure width) and various process conditions (epitaxial thickness, substrate resistivity, well dose). It is demonstrated that with diffused well, latch-up free behavior can be obtained down to 2 μm N+/P+ distance. This immunity to latch-up is ensured either by a holding voltage greater than power supply voltage or by triggering currents high enough.

Published in:

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Date of Conference:

13-16 Sept. 1993