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The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor

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14 Author(s)

POWER7TM the next generation processor of the POWERTM family is introduced. The 8-core chip, supporting 32 threads, is implemented in 45 nm 11 M CMOS SOI. The 32 kB L1 caches feature 1 read port banked write for the l-cache and 2 read ports banked write for the Dcache. The on-chip cache hierarchy consists of a 256 kB fast, private SRAM L2 and a 32MB shared L3, implemented in embedded DRAM.

Published in:

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

Date of Conference:

7-11 Feb. 2010