Referenced Items are not available for this document.
A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed CDR using dithering to avoid excess jitter.
Published in:
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Date of Conference: 7-11 Feb. 2010
- Page(s):
- 160 - 161
- ISSN :
- 0193-6530
- Print ISBN:
- 978-1-4244-6033-5
- INSPEC Accession Number:
- 11204905
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2010.5434008
- Product Type:
- Conference Publications
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