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A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

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7 Author(s)
Reutemann, R. ; Miromico, Zurich, Switzerland ; Ruegg, M. ; Keyser, F. ; Bergkvist, J.
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A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed CDR using dithering to avoid excess jitter.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Date of Conference:

7-11 Feb. 2010