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A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS

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2 Author(s)
Masum Hossain ; Univ. of Toronto, Toronto, ON, Canada ; Anthony Chan Carusone

The clock path in a 65 nm CMOS receiver comprises two injection-locked oscillators to frequency-multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Latency mismatch and data rates are accommodated by controlling jitter tracking up to 300 MHz. Each receiver consumes 0.92 pJ/b at 7.4 Gb/s with a jitter tolerance of 1.5UI at 200 MHz.

Published in:

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

Date of Conference:

7-11 Feb. 2010