Referenced Items are not available for this document.
A 6b 65nm CMOS ADC exceeds the 29GS/S requirement of a 58Gb/s DP-QPSK optical receiver while operating up to 40GS/S. An inter-leaved architecture combines 16 SAR converters and an array of T/Hs with delay, gain, and offset calibration. A 1V 40mW 2.5GS/S subADC results in a total power of 1.5W, ENOB of 4.5b (3.9b) up to 10GHz (18GHz). An on-chip signal synthesizer simplifies production testing.
Published in:
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Date of Conference: 7-11 Feb. 2010
- Page(s):
- 390 - 391
- ISSN :
- 0193-6530
- Print ISBN:
- 978-1-4244-6033-5
- INSPEC Accession Number:
- 11204874
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2010.5433972
- Product Type:
- Conference Publications
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