A 16b 160MS/S pipelined ADC built in a complementary SiGe BiCMOS process is presented, with an SFDR of 105dB and an SNR of 77dB at -1dBFS below 160MHz. The fully buffered track-and-hold has circuitry needed to achieve this performance. The internal sub-DAC uses circuits to mitigate the limitations imposed by transistor self-heating, early voltage and impact ionization.
Published in:
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Date of Conference: 7-11 Feb. 2010