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A 2.2 GS/S 4Ã-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption.
Date of Conference: 7-11 Feb. 2010