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A CMOS frequency multiplier is based on a Pierce oscillator injection-locked by a push-push pair. Compared to traditional stand-alone push-push multipliers driving a selective load, this solution provides a differential output and a larger voltage swing. When driven by a half-frequency VCO, prototypes in 65 nm CMOS demonstrate a 13.1% tuning range at 115 GHz with a phase noise of -107 dBc/Hz @ 10 MHz offset for a total power dissipation of 12 mW.
Date of Conference: 7-11 Feb. 2010