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CMOS phase-locked loops for frequency synthesis

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4 Author(s)
Galton, Ian ; University of California, San Diego, USA ; Razavi, Behzad ; Cowles, John ; Kinget, Peter

As wireless communication systems evolve toward higher frequencies, higher bandwidths, and multi-standard capabilities, the performance of their phase-locked loops (PLLs) becomes increasingly critical to overall system performance. Additionally, PLLs often must be integrated with large digital blocks, so there is strong and increasing economic pressure to implement them in highly-scaled CMOS technology. This short course provides a tutorial explanation of PLL design at both the system and circuit levels in the context of these issues. Topics include integer-N PLLs, fractional-N PLLs, transistor-level design of critical PLL circuit blocks, and practical application-specific PLL issues in a variety of wireless communication systems. The short course is intended for both entry-level and experienced analog, RF, and mixed-signal circuit designers.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Date of Conference:

7-11 Feb. 2010