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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

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9 Author(s)

A 16 KB 8T register-file macro in a 45 nm CMOS process uses on-die PVT-adaptive boosting of read- and write-wordline for minimizing VMN while reducing boosting overhead for maximum power benefit. Measurements of 1 MB 8T arrays in a single-VCC ¿mP core indicate 6 to 27% lower power for arrays access variations of 10% (75 pF) to 30% (1 nF).

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Date of Conference:

7-11 Feb. 2010

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