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An iterative CMOS gate matrix layout algorithm utilising artificial intelligence (A.I.) learning techniques is proposed. This algorithm called GM-Learn, features a rudimentary learning mechanism which enables iterative improvements of the quality of a gate matrix layout. This accomplished through the repetitive applications of a one-pass gate matrix layout algorithm, called GM-Plan, to realise a given circuit specification. The function of GM-Learn, is then to 'learn' to modify the heuristics used in GM-Plan based on the previous trials. Two AI learning paradigms, known as rote learning and learning by parameter adjustment, are employed. These learning techniques enable GM-Learn to modify its heuristic search parameters based on information obtained from previous iterations. Benchmark test results indicate that this novel algorithm is able to produce a high quality gate matrix layout in only a few iterations. The significance of this new method is that it may be applicable to other combinatorial VLSI physical design problems where heuristic guided search is required.