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Terascale chip multiprocessor memory hierarchy and programming model

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9 Author(s)
Shoumeng Yan ; Intel Corp., Santa Clara, CA, USA ; Xiaocheng Zhou ; Ying Gao ; Hu Chen
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Small scale chip multiprocessors are being shipped in volume by all microprocessor vendors. Many of these vendors are also investigating large scale chip multiprocessors targeted towards highly parallel workloads in media, graphics, and others. One of the most challenging aspects of architecting terascale processors is the design of a scalable memory hierarchy. Current proposals for providing coherent shared memory in terascale systems require a sophisticated coherence protocol and memory hierarchy. In this paper we propose an alternate memory configuration along with a programming model that significantly simplifies the terascale memory hierarchy. Our proposal still provides fully coherent shared memory but eliminates the hardware coherence protocol. Our programming model enables the programmer to better express the memory characteristic of terascale workloads. Finally, our proposed memory hierarchy performs better and is more scalable than conventional designs.

Published in:

High Performance Computing (HiPC), 2009 International Conference on

Date of Conference:

16-19 Dec. 2009