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A normally-on 9-kV (at 0.1-mA/cm2 drain leakage) 1.52 ?? 10-3-cm2 active-area vertical-channel SiC JFET (VJFET) is fabricated with no e-beam lithography, no epitaxial regrowth, and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped extension. The VJFET exhibits low leakage currents and a sharp onset of gate-voltage breakdown occurring at 80 V. To lower resistance, the VJFET is designed to be very normally-on, which minimizes the channel resistance contribution. At a gate bias of 0 V, the VJFET's drain current is 73 mA with a forward drain voltage drop of 5 V (240 W/cm2), a specific on-state resistance of 104 m ?? ?? cm2, and a current gain of ID/IG = 6.4 ?? 106. Operating at a unipolar gate bias of 2.5 V lowers the on-state resistance to 96 m ?? ?? cm2 and raises the drain-current output to 79.3 mA, with the current gain being relatively high at ID/IG = 2346. Thus, this 9-kV VJFET is capable of efficient power switching operation with high current gain at a low unipolar resistance.