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A BJT-based 1T-DRAM that utilizes a latch process is analyzed in an experimental assessment. The experimental study reveals that undesired activation of a parasitic BJT by a high leakage current inhibits aggressive scaling of a BJT-based 1T-DRAM. Given the importance of choosing proper operation biases, the drain voltage that triggers the latch process in the BJT-based 1T-DRAM should be reduced to avoid unwanted parasitic BJT activation. Hence, a heterogeneous source and drain is proposed to ensure the energy bandgap offset to silicon channel. A numerical evaluation confirms that a heterogeneous source and drain embedded structure is a promising candidate for high-density and low-power DRAM technologies.