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Organic-Transistor-Based Nano-Floating-Gate Memory Devices Having Multistack Charge-Trapping Layers

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3 Author(s)
Yong-Mu Kim ; Sch. of Adv. Mater. Eng., Kookmin Univ., Seoul, South Korea ; Soo-Jin Kim ; Jang-Sik Lee

Nano-floating-gate memory devices having multistack charge-trapping layers are developed. Controlled gold nanoparticles encapsulated with polyelectrolytes are used as charge-trapping elements. Programmable memory characteristics are observed according to the programming/erasing operations in pentacene-based organic-transistor memory devices. The memory window can be increased effectively by the adoption of multistack charge-trapping layers. The data-retention measurement shows that the programmed/erased states are maintained relatively well according to the time elapsed. This letter is based on simple solution processes at low temperature, so it has a potential use in fabricating nano-floating-gate memory devices on plastic substrates.

Published in:
Electron Device Letters, IEEE  (Volume:31 ,  Issue: 5 )

Date of Publication: May 2010

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