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A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique

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4 Author(s)
Jin-Fu Lin ; Nat. Cheng Kung Univ., Tainan, Taiwan ; Soon-Jyh Chang ; Chun-Cheng Liu ; Chih-Hao Huang

In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-??m 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:57 ,  Issue: 3 )

Date of Publication:

March 2010

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