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Gate-Level Information-Flow Tracking for Secure Architectures

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7 Author(s)
Tiwari, M. ; Univ. of California, Santa Barbara, CA, USA ; Xun Li ; Wassel, H.M.G. ; Mazloom, B.
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This article describes a new method for constructing and analyzing architectures that can track all information flows within a processor, including explicit, implicit, and timing flows. The key to this approach is a novel gate-level information-flow-tracking method that provides a way to create complex logical structures with well-defined information-flow properties.

Published in:

Micro, IEEE  (Volume:30 ,  Issue: 1 )

Date of Publication:

Jan.-Feb. 2010

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