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A Task-Centric Memory Model for Scalable Accelerator Architectures

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5 Author(s)
Kelm, J.H. ; Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Johnson, D.R. ; Lumetta, Steven S. ; Patel, S.J.
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This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors.

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Micro, IEEE  (Volume:30 ,  Issue: 1 )