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Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65 nm standard logic process.