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Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations

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2 Author(s)
Mueller, J.G. ; Electr. & Comput. Eng. Dept., Univ. of British Columbia, Vancouver, BC, Canada ; Saleh, R.A.

Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter budgets. Process, voltage, and temperature variations, especially those that are intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. As a result, active clock deskewing systems are becoming necessary to tune out unwanted clock skew after chip fabrication. This paper first defines the operation of a specially designed phase detector, referred to as an up/down detector (UDD). Next, four of these UDDs are used as links to construct a stable, autonomously locking quadrantal ring tuning (QRT) configuration that effectively joins together four distributed delay-locked loops (DLLs) without the need for any system-level controller. This cyclic, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simplistic two-level QRT system is presented for a generic H-tree clock distribution network, demonstrating stable locking behavior and more than 50% average reduction in overall clock skew.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 6 )