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Selective Access to Filter Cache for Low-Power Embedded Systems

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2 Author(s)
Jong Wook Kwak ; Dept. of Comput. Eng., Yeungnam Univ., Gyeongsan, South Korea ; Ju Hee Choi

Filter cache has been introduced as one solution of reducing cache power consumption. When the filter cache is utilized in a memory system, more than 50% of the power reduction is accomplished due to the filter cache. However, more than 20% of the performance is compromised as well. To minimize the performance loss of the filter cache, this paper proposes a new filter cache predictor model and its algorithm. In our scheme, Mode Selection Bit (MSB) controls selective accesses to a filter cache and a Branch Target Buffer (BTB). The simulation result shows that our solution provides performance improvement, in energy-delay product, up to about 9.1%, compared to previous policies.

Published in:

System Sciences (HICSS), 2010 43rd Hawaii International Conference on

Date of Conference:

5-8 Jan. 2010