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Improved Area-Efficient Weighted Modulo 2^{n} + 1 Adder Design With Simple Correction Schemes

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3 Author(s)
Tso-Bing Juang ; Dept. of Comput. Sci. & Inf. Eng., Nat. Pingtung Inst. of Commerce, Pingtung, Taiwan ; Chin-Chieh Chiu ; Ming-Yu Tsai

In this brief, we proposed improved area-efficient weighted modulo 2n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n - 1} produced by existing diminished-1 modulo 2n + 1 adders. We have implemented the proposed adders using 0.13-??m CMOS technology, and the area required for our adders is lesser than previously reported weighted modulo 2n + 1 adders with the same delay constraints.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:57 ,  Issue: 3 )